Figure 10
From: Synthesizing genetic sequential logic circuit with clock pulse generator

Topology of the synchronous genetic counter for the clock signal with triple basal period. (a) Clock pulse signal from low to high; (b) Clock pulse signal from high to low; (c) Output signal of the first genetic JK flip-flop; (d) Output signal of the second genetic JK flip-flop; (e) Output signal of the third genetic JK flip-flop; and (f) Output signal of logic OR of (d) and (e).