Figure 10From: Synthesizing genetic sequential logic circuit with clock pulse generator Topology of the synchronous genetic counter for the clock signal with triple basal period. (a) Clock pulse signal from low to high; (b) Clock pulse signal from high to low; (c) Output signal p Q 1 of the first genetic JK flip-flop; (d) Output signal p Q 2 of the second genetic JK flip-flop; (e) Output signal p Q 3 of the third genetic JK flip-flop; and (f) Output signal of logic OR of (d) and (e).Back to article page